Temporal Reasoning for Network Acceleration
Effectively combining performance with flexibility requires support in both hardware and software. Matching the capabilities of both is hard, and engineering solutions commonly rely on well-established interfaces and APIs such as a microprocessor's assembly language, an FPGA's bitstream format, or a network processor's API. We are exploring ways to unify these interfaces, in particular, to make it straightforward to build data center services that exploit programmable hardware as easily as traditional hardware, interoperating with existing services running on a range of platforms. Work supported by EPSRC grant references EP/K031724/2 and EP/K034723/1.